The present invention relates generally to a phase change memory device, and more particularly to a technology of activating a dummy cell array configured to form a discharging path of a bit line in an active mode to prevent an excessive leakage current in a precharge mode.
A nonvolatile memory has a data processing speed similar to that of a volatile Random Access Memory (RAM), however, unlike a volatile RAM, a nonvolatile memory conserves data even when no power is supplied to the memory, that is, after the power is turned off.
FIGS. 1a and 1b are diagrams showing a conventional phase change resistor (PCR) 4.
The PCR 4 comprises a phase change material (PCM) 2 inserted between an upper electrode 1 and a lower electrode 3. When a voltage and a current are applied to the PCR 4, a high temperature is generated in the PCM 2 such that an electric conductive state of the PCR 4 is changed depending on the resistance of the PCM 2. The PCM may comprise AgLnSbTe. The PCM 2 may also comprise chalcogenide having chalcogen elements (S, Se, Te) as a main ingredient, for example, a germanium antimonic tellurium consisting of Ge—Sb—Te.
FIGS. 2a and 2b are diagrams showing the principle operation of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can be crystallized when a low current, i.e., a current less than a threshold value, flows through the PCR 4. As a result, the PCM2 becomes a crystalline phase, that is the PCM 2 becomes a low resistance material.
As shown in FIG. 2b, the PCM 2 can be amorphized when a high current, i.e., a current higher than a threshold value, flows through the PCR 4. That is, the temperature of the PCM 2 is increased higher than its melting point when a high current flows through the PCR 4. As a result, the PCM 2 becomes an amorphous phase, that is, the PCM 2 becomes a high resistance material.
In this way, the PCR 4 is configured to store nonvolatile data corresponding to the two resistance states. That is, data “1” refers to a low resistance state of the PCR 4, and data “0” refers to a high resistance state of the PCR 4 so that the data can be stored to have one of the two logic states.
FIG. 3 is a diagram showing a write operation of a conventional phase change resistant cell.
Heat is generated when a current flows through the upper electrode 1 and the lower electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 is changed to be either the crystalline phase or the amorphous phase depending on the current applied to the upper electrode 1 and the lower electrode 3.
A low temperature heating state occurs when a low current flows through the upper electrode 1 and the lower electrode 3 for a given time. As a result the PCM 2 becomes the crystalline phase and the PCR 4, which acts as a low resistor, is at a set state. On the other hand, a high temperature heating state occurs when a high current flows between the upper electrode 1 and the lower electrode 3 for a given time. As a result, the PCM 2 becomes the amorphous phase and the PCR 4, which acts as a high resistor, is at a reset state. Therefore, the two different phases are represented by the change of the electric resistance of the PCR 4.
As shown in FIG. 3, a low voltage is applied to the PCR 4 for a period of time in order to write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a shorter period of time in order to write the reset state in the write mode.
FIG. 4 is a diagram illustrating a cell array of a conventional phase change memory device.
As shown in FIG. 4, a conventional phase change memory device includes a plurality of unit cells C positioned at the intersections of a plurality of bit lines BL1˜BL4 and a plurality of word lines WL1˜WL4. Each unit cell C may include a phase change resistor PCR and a diode D. The diode D may include a PN diode element.
In the unit cell C, a first electrode of the PCR is connected to the bit line BL1 and a second electrode of the PCR is connected to a P-type region of the diode D. Further, an N-type region of the diode D is connected to the word line WL1.
In a read mode, a low voltage may be applied to a selected word line WL and a read voltage Vread may be applied to the bit line BL. As a result, a read current Iset having a set state or a read current Ireset having a reset state may flow towards the word line WL through the bit line BL, the PCR, and the diode D.
A sense amplifier S/A senses cell data received from a bit line BL, and compares the cell data with a reference voltage Vref to distinguish data “1” from data “0”. A reference current Iref may flow in a terminal for receiving the reference voltage Vref. A write driving unit W/D supplies a driving voltage corresponding to write data to the bit line BL when data are written in a unit cell C.